Memory element and method for fabricating a memory element

ABSTRACT

A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.

The invention relates to a memory element and to a method forfabricating a memory element.

A memory element of this type and a method for fabricating a memoryelement of this type are known from [1].

In the memory element which is known from [1], organic complexes areprovided for the purpose of electrically coupling first lines in a firstmetallization layer to second lines in a second metallization layer.However, the organic complexes are introduced into the memory elementduring the individual fabrication processes for the further componentsof the memory element, in particular prior to the fabrication of atleast some of the wiring planes and metallization layers and of thecorresponding contacts.

Examples of organic complexes of this type whose electrical conductivitycan change by up to a factor of 10⁴ on account of an electric voltagewhich is applied to the organic complexes, i.e. to the organic material,are known, for example from [2], asN-(3-nitrobenzylidene)-p-phenylenediamine (NBPDA) or as a system of thetwo materials 3-nitrobenzal-malononitrile (NBMN) and1,4-phenylenediamine (pDA).

A further organic material which changes its electrical conductivity asa result of an electric voltage applied to the material is known from[3] as rotaxane.

These organic materials are highly sensitive and can easily be damaged,in particular with regard to their behaviour in terms of changing theirelectrical conductivity.

One drawback of the memory element which is known from [1] is thereforeto be seen in particular as residing in the fact that the organicmaterial which is introduced during the method steps, which in somecases are carried out under a great heat, as part of the fabricationmethod of the memory element, for example during a silicon process, isvery easily damaged by the heat.

Therefore, an organic memory element of this type is highly susceptibleto faults and its electrical properties are not very robust.

Furthermore, [4] has disclosed a memory cell arrangement and its use asa magnetic RAM memory element and as an associative memory.

Furthermore, [4] has disclosed a drive circuit for the individual memorycells of the magnetic RAM memory element, for writing and reading binaryinformation into and from the respective memory cells via word lines andbit lines.

[5] describes a memory arrangement having a film of organic material.

[6] describes a ROM having a substrate, to which substrate electrodesare applied. A layer is arranged between the electrodes. The ROMconsists of conjugated polymers or oligomers and doping atoms.

Further electrically addressable storage media are described in [7],[8], [9], [10], [11], [12] and [13].

Therefore, the invention is based on the problem of describing a memoryelement with organic materials and a method for fabricating a memoryelement of this type, which memory element has a reduced susceptibilityto faults compared with the memory element which is known from [1].

A memory element has a substrate in which individual transistors andelectrical components of the memory element are usually already present.A first metallization layer, preferably of gold, is applied to thesubstrate, for example a silicon substrate, and a first insulation layeris applied to the first metallization layer. A second metallizationlayer, which preferably likewise consists of gold, is applied to thefirst insulation layer, which is preferably made from plasma dioxide orplasma nitride.

The first metallization layer and the second metallization layer arearranged above one another in parallel planes, so that the individualmetallization layers do not touch one another. The first metallizationlayer is patterned in such a manner that first electric lines, which arein each case electrically insulated from one another by, for example,the first insulation layer, are formed therein.

Furthermore, second electric lines, which are arranged above the firstelectric lines of the first metallization layer in such a manner thatthey cross one another but, on account of the first insulation layerarranged between them, are not in electrical contact with one another,are formed in the second metallization layer.

At at least some of the crossing points between the first line and asecond line, there is in each case one trench, which at least partiallyoverlaps the first line and directly couples, preferably completelyoverlaps, the second line.

The term crossing point is to be understood as meaning, for example, apoint at which, as a result of a substantially perpendicular beingraised on one of the two lines, in each case the other line is alsotouched.

Each trench, or at least some of the trenches, is/are filled with anorganic filler material, the electrical conductivity of which can bechanged by an applied electric voltage. The change should besufficiently strong and enduring for it to be easily and robustlypossible to record two different states of the organic material,according to whether there is a voltage applied or no voltage applied,in order reliable writing and reading of binary information to and fromthe respective memory cell is ensured.

In this context, all organic materials whose electrical conductivity maychange in particular by up to a factor of 10⁴, preferably by up to afactor of 10³ or 10², are suitable.

The filler material may therefore include, for example, organiccomplexes, preferably the materials

rotaxane, and/or

N-(3-nitrobenzylidene)-p-phenylenediamine (NDPDA), and/or

a system of the materials 3-nitrobenzal-malononitrile (NBMN) and1,4-phenylenediamine (pDA)

which are known from [2] and [3].

Beneath the two metallization layers, i.e., for example, between themetallization layers and the substrate or even beneath the substrate,there may be a peripheral electronic circuit, which enables the memoryelement, in particular the individual memory cells which are formed byin each case a filler material with which a trench has been filled, torespond unambiguously and in a highly robust and fault-insensitive way,for example by a binary value being written to or read from a memorycell.

In this memory element, the binary information is given by thecorresponding conductivity of the filler material which is arranged inthe trenches between the two lines, which represent the word lines andbit lines of the memory element.

The result is a memory element with organic complexes which isunsusceptible to faults and has a very high integration density, since amemory cell has a minimum space requirement of 4*F*F (F=feature size),i.e. in each case the minimum patterning size of the fabrication processused.

If gold is used for the individual lines, one advantage of the memoryelement is, inter alia, that, by means, for example, of the knowngold-sulphur coupling, the corresponding organic materials bond verywell to the electric lines, in particular by means of a covalent bond.

A further advantage when using gold for the individual lines is that thesurfaces of the individual lines are not oxidized or are only oxidizedto a very minor extent.

The memory element has the advantage in particular that the organiccomplexes only have to be incorporated after the silicon processing,with the result that damage to the organic material under a hightemperature load which is required for individual silicon elementfabrication steps does not occur.

Since the entire peripheral circuit may be arranged beneath therespective cell field, the chip surface area which remains active, i.e.is completely available for the memory element, is increased further.

The memory element may have additional wiring layers, in order for theindividual electronic components provided in the silicon substrate to beelectronically coupled to one another.

Furthermore, a second insulation layer may be provided between thesubstrate and the first metallization layer, in order for the substrateand the first metallization layer, i.e. in particular the first electriclines, to be electrically insulated from one another.

In a method for fabricating a memory element, a first metallizationlayer is applied to a substrate and is patterned in such a manner thatfirst lines are formed, which are brought into electrical contact withthe substrate. This can be achieved, for example, by forming contactholes between the first lines and the substrate, through a secondinsulation layer provided between them, so that electrical contact canbe made between the first lines and the substrate. A first insulationlayer is applied to the first metallization layer, and a secondmetallization layer is applied to the first insulation layer and ispatterned in such a manner that second lines are formed, which althoughthey do not electrically couple the first lines do cross them above thefirst lines. At least at some of the crossing points between the firstlines and the second lines, a trench is formed, which in each casepartially overlaps the first line and couples the second line, i.e.preferably completely overlaps the second line. The trenches are filledwith a filler material, for example an organic filler material asdescribed above, so that the first lines and the second lines can ineach case be electrically coupled to one another via the fillermaterial. As explained above, the filler material has a conductivitywhich changes considerably as a result of an applied electric voltage.

An exemplary embodiment of the invention is illustrated in the figuresand is explained in more detail below. In the figures:

FIGS. 1a to 1 d in each case show a cross section through a memoryelement at different times during its fabrication.

FIG. 1a shows a substrate 101, in which the individual electroniccomponents which are necessary for a memory element in order to activatethe latter, in particular the MOS field-effect transistors (not shown)which are required, are already present.

A chemical vapour deposition (CVD) method or alternatively a sputteringmethod or a physical vapour deposition method is used to apply a firstinsulation layer 102, preferably of silicon nitride, to the substrate101, which according to the present exemplary embodiment is made fromsilicon.

The first insulation layer 102 has a thickness of approximately 300 nmto 700 nm; in this context, it should be noted that the thickness of thefirst insulation layer 102 is essentially of little importance for theway in which the invention functions and can be selected as desired.

Contact holes 104 are etched after a first photolithography method.Then, trenches with a depth of approximately 100 nm to 200 nm are etchedinto the insulation layer 102.

Furthermore, if a deposition method from a liquid is used in asubsequent step, an electrically conductive layer is deposited on thefirst insulation layer 102.

In a further step, a first metallization layer 103 of gold is applied tothe first insulation layer 102 or the electrically conductive layer,preferably by means of a deposition method from a liquid(electroplating), or alternatively by means of a sputtering method or avapour deposition method.

During the deposition of the gold, or in general terms of the metal forforming the first metallization layer 103, the contact holes 104 and thetrenches are filled with gold.

A chemical mechanical polishing method (CMP method) is used to form thefirst metallization layer 103, in that sufficient gold is removed forthe gold to be present only in the trenches. In this way, the conductortracks in the first metallization layer 103 are electrically separatedfrom one another.

As shown in FIG. 1b, a second insulation layer 105, which according tothis exemplary embodiment comprises nitride, is then applied to thefirst metallization layer 103, by means of a CVD method, a physicalvapour deposition method or a sputtering method.

After a further photolithography method, contact holes are in turnetched into the second insulation layer 105.

In a further step, the second insulation layer 105 is patterned by meansof photolithography, in such a manner that trenches 106 are etched intoit, in which trenches, in a subsequent method step, after removal of thephotoresist used for the photolithography, a second metallization layer107 is formed, which according to the present exemplary embodiment isonce again formed from gold.

During the deposition of the gold, both the contact holes and thetrenches 106 are filled with gold.

A subsequent CMP method is used to remove the protruding gold, so thatgold is then only present in the trenches 106. As a result, theconductor tracks which are formed in the second metallization layer 107are electrically separated from one another. The second metallizationlayer 107 which is formed has a thickness of approximately 200 nm.

The second metallization layer 107 is formed by means of anelectroplating method, a sputtering method or a physical vapourdeposition method, and the trenches 106 are at least partially formed inaccordance with the second patterning as second metallization layer 107.

When using an electroplating method to form the second metallizationlayer 107, a further electrically conductive layer is deposited on thesecond insulation layer 105 prior to the electroplating.

The trenches 106 are formed in the second insulation layer 105 in such amanner that the thickness of the second insulation layer 105 between thebase 108 of a respective trench 106 and the upper surface 109 of thefirst metallization layer 103 is approximately 100 nm.

In a further step, photolithography is used to generate a mask, intowhich, in a further step, a multiplicity of holes 110 is introduced bymeans of dry etching. The holes 110 are formed only at first lines andsecond lines which cross one another.

The etched holes 110 or trenches 110 are arranged in such a manner inthe memory element 100 which is formed (cf. FIG. 1c) that they make fullelectrical contact with the first lines of the first metallization layer103 and penetrate partially through the second lines of the secondmetallization layer 107, for example as a result of an edge region or,in general, a partial region of a second line being removed by etchingof the respective trench 110.

The trenches 106 preferably have a diameter of approximately 50 nm to100 nm; in the case of rectangular trenches, the respective sides of atrench 110 are in each case approximately 50 nm to 100 nm.

In this context, it should be noted that only a part of the second lineis removed by in each case one trench 110, so that a second line whichis sufficient to provide appropriate electrical conductivity remains inplace, which second line can be brought into electrical contact with therespective first electrical line of the first metallization layer 103 bymeans of an organic material which has been introduced in a step whichis explained below.

Then, the photoresist is removed, after the trenches 110 have beenetched through both the second metallization layer 107 and through thesecond insulation layer 105.

In a final step, N-(3-nitrobenzylidene)-p-phenylenediamine is depositedin the trenches 110 as filler material 111, using the method describedin [2].

Alternatively, the method described in [3] can be used to depositrotaxane as filler material 111 in the memory element 110 illustrated inFIG. 1d.

In a final step, the filler material 111 which projects above thetrenches 110 is etched back, i.e. removed.

According to the exemplary embodiment, the first lines form the wordlines and the second lines form the bit lines of the memory element 100.

The activation circuit of the individual memory cells of the memoryelement 100, which are formed by the word lines and bit lines of thefirst metallization layer 103 and second metallization layer 107,respectively, and the trenches 110 filled with the filler material 111,according to the present exemplary embodiment, is designed in the sameway as that described in [4].

The following publications are cited in this document:

[1] R. F. Service, Organic Molecule Rewires Chip Design, Science, Vol.285, pp. 313-315, 16 Jul. 1999

[2] H. J. Gao et al., Reversible, Nanometer-Scale ConductanceTransitions in an Organic Complex, Physical Review Letters, Vol. 84, No.8, pp. 1780-1783, February 2000

[3] C. P. Collier et al., Electronically Configurable Molecular-BasedLogic Gates, Science 285, pp. 391-394, 1999

[4] WO 99/14760 A1

[5] DE OS 2 314 193

[6] WO 97/30445

[7] U.S. Pat. No. 6,055,180

[8] U.S. Pat. No. 6,072,716

[9] U.S. Pat. No. 4,876,668

[10] U.S. Pat. No. 4,371,883

[11] JP 08-116 109 A

[12] JP 06-222 4961 A

[13] JP 04-414 5664 A

LIST OF REFERENCE SYMBOLS

100 Memory element

101 Substrate

102 First insulation layer

103 First metallization layer

104 Contact hole

105 Second insulation layer

106 Trench

107 Second metallization layer

108 Bottom of trench

109 Surface of first metallization layer

110 Trench

111 Filler material

What is claimed is:
 1. Memory element having a substrate, having a firstmetallization layer, having a second metallization layer, in which thefirst metallization layer and the second metallization layer arearranged above one another in parallel planes, a first insulation layerbeing arranged between the first metallization layer and the secondmetallization layer, first lines in the first metallization layer andsecond lines in the second metallization layer being arranged so thatthey cross one another, in which a trench, which partially overlaps thefirst line and couples the second line, is formed at at least some ofthe crossing points between the first line and the second line, and inwhich the trench is filled with a filler material, the electricalconductivity of which can be changed by an applied electric voltage. 2.Memory element according to claim 1, in which the filler materialincludes organic complexes.
 3. Memory element according to claim 2, inwhich the filler material includes at least one of the followingmaterials: rotaxane, N-(3-nitrobenzylidene)-p-phenylenediamine (NBPDA),and/or a system comprising the materials 3-nitrobenzal-malononitrile(NBMN) and 1,4-phenylenediamine (pDA).
 4. Memory element according toone of claims 1 to 3, in which the substrate contains silicon.
 5. Memoryelement according to one of claims 1 to 4, in which the firstmetallization layer and/or the second metallization layer contains gold.6. Memory element according to one of claims 1 to 5, in which aperipheral electronic circuit is arranged beneath the trench.
 7. Memoryelement according to one of claims 1 to 6, having at least one firstwiring layer, and having at least one second wiring layer.
 8. Memoryelement according to one of claims 1 to 7, in which a second insulationlayer is provided between the substrate and the first metallizationlayer.
 9. Memory element according to one of claims 1 to 8, in which thefirst insulation layer and/or a second insulation layer which isprovided between the substrate and the first metallization layercontains silicon nitride or silicon dioxide.
 10. Method for fabricatinga memory element, in which a first metallization layer is applied to asubstrate and is patterned in such a manner that first lines are formed,which are brought into electrical contact with the substrate, in which afirst insulation layer is applied to the first metallization layer, inwhich a second metallization layer is applied to the first insulationlayer and is patterned in such a manner that second lines are formed,which cross the first lines, in which a trench, which partially overlapsthe first line and couples the second line, is formed at at least someof the crossing points between a first line and a second line, in whichthe trench is filled with a filler material, the electrical conductivityof which can be changed by an applied electric voltage.
 11. Methodaccording to claim 10, in which organic complexes are used as fillermaterial.
 12. Method according to claim 11, in which, the fillermaterial used is at least one of the following materials: rotaxane,N-(3-nitrobenzylidene)-p-phenylenediamine (NBPDA), and/or a systemcomprising the materials 3-nitrobenzal-malononitrile (NBMN) and1,4-phenylenediamine (pDA).
 13. Method according to one of claims 10 to12, in which the substrate used is silicon.
 14. Method according to oneof claims 10 to 13, in which gold is used for the first metallizationlayer and/or the second metallization layer.
 15. Method according to oneof claims 10 to 14, in which a second insulation layer is introducedbetween the substrate and the first metallization layer.
 16. Methodaccording to one of claims 10 to 15, in which contact holes are formedthrough the second insulation layer, between the first lines and thesubstrate.